The present invention relates generally to the fabrication of integrated circuits (IC""s), and more particularly to the fabrication of memory IC""s.
Semiconductor devices are used in a variety of electronic applications, such as personal computers and cellular phones, for example. The semiconductor industry in general is being driven to decrease the size of semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today""s semiconductor products.
One semiconductor product widely used in electronic systems for storing data is a semiconductor memory device, and one common type of semiconductor memory device is a dynamic random access memory (DRAM). A DRAM typically includes millions or billions of individual DRAM cells arranged in an array, with each cell storing one bit of data. A DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
DRAM storage capacitors are typically formed by etching deep trenches in a substrate. A plurality of layers of conductive and insulating materials are deposited in order to produce a storage capacitor that is adapted to store a bit of data, represented by a one or zero. Prior art DRAM designs typically comprise an access FET disposed in a subsequent layer to the side of the storage capacitor. More recent DRAM designs involve disposing the access FET directly above the storage capacitor in the upper part of the trench, which conserves surface area, resulting in the ability to place more DRAM cells on a single chip.
An element known a buried strap is a conductive path that electrically couples a memory cell storage capacitor to the drain of an access transistor. In vertical access transistor technology, the capacitor is formed in the lower part of the trench, and the access transistor is formed in the upper part of the trench. A thick dielectric layer called trench top oxide (TTO) forms the electrical isolation between capacitor and transistor. The strap is buried below the wafer surface in the trench sidewall below the TTO. Dopant outdiffusion from the strap into the silicon sidewall creates a doped area and forms the drain of the access transistor. Prior art buried strap formation typically involves a trench top oxide deposition in the upper part of the trench. The typical TTO comprises tetraethoxysilane (TEOS) that, when deposited, is thicker on the bottom than on the sides. Having TEOS on the sides of the trenches of a DRAM storage cell is undesirable, and requires additional processing steps to remove the TTO from the trench sidewalls. A TTO sidewall etch typically requires a wet etch that causes the TTO remaining within the trench to have a high degree of non-uniformity. Furthermore, a TTO TEOS deposition does not permit adequate control of the thickness of the TTO. Precise thickness control of the TTO is necessary because the outdiffused area from the buried strap must, on one hand, extend above the vertical gate oxide of the access transistor, and on the other hand, it must not merge with outdiffused regions from neighboring trenches which causes floating body effects.
What is needed in the art is a method of forming a buried strap that allows for improved control of the TTO thickness and has a reduced number of processing steps than in prior art TEOS TTO depositions.
Embodiments of the present invention achieve technical advantages as a method forming a buried strap of a memory cell that does not require a TEOS deposition process for the formation of TTO. A semiconductor material is deposited over and within trenches. A vertical dopant implant dopes the top surface, and not the sidewalls, of the semiconductor material within the trenches. The undoped semiconductor material is removed from the trench sidewalls, and the doped semiconductor material remaining within the trenches is oxidized in a thermal oxidation process.
Disclosed is a method of manufacturing a semiconductor memory cell, comprising providing a semiconductor wafer having a substrate, forming a plurality of trenches in the substrate, forming capacitor structures in the lower part of the trenches and a collar oxide in the top part of the trench, , and filling the trench with a first semiconductor material. The method includes removing a top portion of the semiconductor material, leaving a portion of the first semiconductor material remaining within the trenches, and removing a top portion of the collar oxide layer. Using an overetch process, the collar oxide is recessed to a level below the top of the first semiconductor material within the trenches and forms a divot. The method includes forming a thin nitride layer over the exposed semiconductor substrate within the trenches, depositing a second semiconductor layer over the nitride layer, and exposing the wafer to a vertical dopant implantation process to dope the top surfaces and the horizontal surface inside the trench of the second semiconductor layer, leaving the second semiconductor layer undoped on the sidewalls of the trenches. The undoped second semiconductor layer is removed from the trench sidewalls, and the doped second semiconductor layer disposed over the first semiconductor material is oxidized.
Also disclosed is a method of forming a buried strap for a vertical DRAM having a plurality of trenches formed in a substrate on a semiconductor wafer. The method includes depositing a first oxide layer over the substrate, depositing a first semiconductor material in the trenches to a height below the top surface of the substrate, removing a top portion of the first oxide layer to a level below the top of the first semiconductor material within the trenches, and forming a nitride layer over the exposed semiconductor substrate on the trench sidewalls. The method includes depositing a second semiconductor layer over the nitride layer, doping the top surfaces of the second semiconductor layer, leaving the second semiconductor layer undoped on the trench sidewalls, removing the undoped second semiconductor layer from the trench sidewalls, and oxidizing the doped second semiconductor layer over the first semiconductor material to form an oxide region within the doped second semiconductor layer.
Further disclosed is a method of processing a semiconductor device, comprising depositing a first oxide layer over a substrate, the substrate having trenches formed therein. A first semiconductor material is deposited over the first oxide layer, and a top portion of the semiconductor material is removed, leaving a portion of the first semiconductor material remaining within the trenches. The method includes removing a top portion of the first oxide layer to a level below the top of the first semiconductor material within the trenches, forming a nitride layer over the exposed semiconductor substrate within the trenches, and depositing a second semiconductor layer over the nitride layer. The top surfaces of the second semiconductor layer are doped, leaving the second semiconductor layer undoped on the sidewalls of the trenches. The undoped second semiconductor layer is removed from the trench sidewalls, and the doped second semiconductor layer disposed over the first semiconductor material is oxidized.
Advantages of embodiments of the invention include providing a method of forming a buried strap that does not require a TEOS deposition or a sidewall wet etch to remove TEOS TTO from the trench sidewalls, as in the prior art. Embodiments of the present invention result in improved thickness control and uniformity of buried strap TTO, permit reduction of buried strap outdiffusion, and result in reduced floating body effects.